Non-volatile memory (NVM) arrays are used to store data as a plurality of bit states, in a medium that maintains the data without the need for a continuous supply of electrical power. FIG. 1 is a schematic diagram of one embodiment of a conventional NVM array 10 having a plurality of memory cells provided as a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors 20a-20g. Each of transistors 20a-20g has a control gate, a drain, and a source. The NVM array 10 is configured as a “virtual ground array,” in which the drain of each one of transistors 20a-20f is directly coupled to the source of the next transistor 20b-20g, respectively, forming a chain of transistors 20a-20g that eliminates the need for an area-consuming ground contact for the source of each of the transistors 20a-20g. For each stored bit state of each of transistors 20a-20g, a predetermined amount of electric charge is programmed in a memory layer of the transistor, such as a floating gate or charge trapping layer of the transistor. This electric charge creates an electric field that alters an effective threshold voltage VT of the transistor that depends on the bit state of the transistor.
With reference to FIG. 1, a bit state of a selected transistor 20b is evaluated by a bit sensor 30 and a voltage supply 40 that together apply a voltage between the drain and the source of the selected transistor 20b. A current ICELL, whose direction is indicated by the hollow arrow 50, is induced through the selected transistor 20b and has a magnitude that is a function of the effective threshold voltage VT of the selected transistor 20b. The bit sensor 30 comprises a comparator (not shown) that compares the selected transistor's effective threshold voltage VT to a reference voltage to evaluate the bit state of the selected transistor 20b. 
However, when measuring the current between the drain and source of the selected transistor 20b, a portion of current ICELL leaks as a current IL into the neighboring transistors 20c-20g. As a result, the bit sensor 30 measures a current IREAD that is reduced by the leakage current IL, rather than the full drain-to-source current ICELL of the selected transistor 20b, potentially resulting in an incorrect evaluation of the bit state of the selected transistor 20b. Moreover, the leakage current IL may vary, depending on, for example, the location of the selected transistor 20b or the effective threshold voltage of one of the downstream transistors 20c-20g within the NVM array 15.
Thus, it is desirable to accurately read stored data from cells of a non-volatile memory array. It is further desirable to have a non-volatile memory package including a non-volatile memory array from which programmed data can be accurately read.